Since our project has changed significantly, our proposal’s goals do not at all reflect our current goals and deliverables, but we do have a more concrete approach to what we want accomplished.
Our performance metrics will be seen through a decrease in cache misses in the Last Level Cache shared between the multi-core processor simulated in gem5 along with an increase in performance in terms of clock ticks for our specified benchmarks.
The benchmarks we use will come in three different stages: no memory access, basic memory access, and complex memory access patterns. We hope to see a significant difference between all three especially when we know where to insert the prefetches due to the simulator.